1. Field of the Invention
The present invention is related to verification of circuit simulation trace file results, and in particular, to techniques for handling trace file results that are segmented into multiple output files to reduce storage and addressing requirements.
2. Description of Related Art
Logic simulators, including emulators and accelerators that can be implemented in hardware, software or a combination of both, are typically are used in verification of designs of processor integrated circuits (ICs), as well as other large-scale logic. The logic simulators generate a simulation output representing the behavior of the hardware being simulated. Checkers then check certain behaviors (events) in the simulation output and verify that the detected events correspond to expected causative events and/or that all events that should cause a resulting event have a corresponding correct resulting event. Verification can either be performed on-line, in which checking is performed on the trace, or off-line, in which the trace is stored in a file and processed later.
With the large and complex devices available today, the off-line trace output files can easily become unwieldy, for example, the size of a resulting trace file may exceed a computer system's maximum file size. Further, the efficiency of algorithms that perform the above-described event-checking can be dependent on the amount of memory occupied by the data being analyzed and the fact that a sequential process such as simulation does not lend itself to parallel processing.
Solutions of the above problem typically reduce the size of the resulting trace file by sampling, i.e., by not exhaustively verifying the design. Therefore, an alternative technique for off-line verification is desired.